XC2C256-7PQG208C
Manufacturer: Xilinx Inc.
By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching.
Another feature that eases voltage translation is I/O banking. Two I/O banks are available on the CoolRunner-II 128 macrocell device that permit easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices.
The CoolRunner-II 128 macrocell CPLD is I/O compatible with various JEDEC I/O standards (see Table 1). This device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs.
Table 1: I/O Standards for XC2C128(1)
IOSTANDARD AttributeOutput VCCIOInput VCCIOInput VREFBoard Termination Voltage VTTLVTTL3.33.3N/AN/ALVCMOS333.33.3N/AN/ALVCMOS252.52.5N/AN/ALVCMOS181.81.8N/AN/ALVCMOS15(2)1.51.5N/AN/AHSTL_11.51.50.750.75SSTL2_12.52.51.251.25SSTL3_13.33.31.51.5
Feature
• Optimized for 1.8V systems
- As fast as 5.7 ns pin-to-pin delays
- As low as 13 μA quiescent current
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis.
Refer to the CoolRunner™-II family data sheet for
architecture description.
- Multi-voltage I/O operation — 1.5V to 3.3V
• Available in multiple package options
- 100-pin VQFP with 80 user I/O
- 144-pin TQFP with 118 user I/O
- 132-ball CP (0.5mm) BGA with 106 user I/O
- 208-pin PQFP with 173 user I/O
- 256-ball FT (1.0mm) BGA with 184 user I/O
- Pb-free available for all packages
Stock:8573
Minimum Order:1
By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching.
Another feature that eases voltage translation is I/O banking. Two I/O banks are available on the CoolRunner-II 128 macrocell device that permit easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices.
The CoolRunner-II 128 macrocell CPLD is I/O compatible with various JEDEC I/O standards (see Table 1). This device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs.
Table 1: I/O Standards for XC2C128(1)
IOSTANDARD AttributeOutput VCCIOInput VCCIOInput VREFBoard Termination Voltage VTTLVTTL3.33.3N/AN/ALVCMOS333.33.3N/AN/ALVCMOS252.52.5N/AN/ALVCMOS181.81.8N/AN/ALVCMOS15(2)1.51.5N/AN/AHSTL_11.51.50.750.75SSTL2_12.52.51.251.25SSTL3_13.33.31.51.5
Feature
• Optimized for 1.8V systems
- As fast as 5.7 ns pin-to-pin delays
- As low as 13 μA quiescent current
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis.
Refer to the CoolRunner™-II family data sheet for
architecture description.
- Multi-voltage I/O operation — 1.5V to 3.3V
• Available in multiple package options
- 100-pin VQFP with 80 user I/O
- 144-pin TQFP with 118 user I/O
- 132-ball CP (0.5mm) BGA with 106 user I/O
- 208-pin PQFP with 173 user I/O
- 256-ball FT (1.0mm) BGA with 184 user I/O
- Pb-free available for all packages
